Design and implementation of a single-chip 1-d median filter
Journal Article
·
· IEEE Trans. Acoust., Speech, Signal Process.; (United States)
The design and implementation of a VLSI chip for the one-dimensional median filtering operation is presented. The device is designed to operate on 8-bit sample sequences with a window size of five samples. Extensive pipelining and employment of systolic data-flow concepts at the bit level enable the chip to filter at rates up to ten megasamples per second. A configuration for using the chip for approximate two-dimensional median filtering operation is also presented. 16 references.
- Research Organization:
- Carnegie-Mellon Univ., Pittsburgh, PA
- OSTI ID:
- 5170646
- Journal Information:
- IEEE Trans. Acoust., Speech, Signal Process.; (United States), Journal Name: IEEE Trans. Acoust., Speech, Signal Process.; (United States) Vol. 5; ISSN IETAB
- Country of Publication:
- United States
- Language:
- English
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