Fast parallel algorithm for ternary multiplication using multivalued I2L technology
Journal Article
·
· IEEE Transactions on Computers (Institute of Electrical and Electronics Engineers); (United States)
- Kalyani Univ., Kalyana (India)
n algorithm for parallel multiplication of two n-bit ternary numbers is presented in this brief contribution. This algorithm uses the technique of column compression and computes the product in (2(log(sub 2) n) + 2) units of addition time of a single-bit ternary full adder. This algorithm requires regular interconnection between any two types of cells and hence is very suitable for VLSI implementation. The same algorithm is also applicable to the multiplication of negative numbers. 28 refs.
- OSTI ID:
- 6687658
- Journal Information:
- IEEE Transactions on Computers (Institute of Electrical and Electronics Engineers); (United States), Journal Name: IEEE Transactions on Computers (Institute of Electrical and Electronics Engineers); (United States) Vol. 43:5; ISSN ITCOB4; ISSN 0018-9340
- Country of Publication:
- United States
- Language:
- English
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