Fast parallel algorithms for binary multiplication and their implementation on systolic architectures
Journal Article
·
· IEEE Trans. Comput.; (United States)
Two algorithms for parallel multiplication of two n-bit binary numbers have been presented in this paper. The first algorithm computes the product of a single-bit full adder and is easily implementable on the n x n systolic SIMD architecture. The second algorithm is still faster. Both the algorithms require almost regular interconnection between only two types of cells and hence are very suitable for VLSI implementation. Both of them can also be easily modified to handle two's complement numbers with constant difference in time.
- Research Organization:
- Dept. of Computer Science, Southern Illinois Univ., Carbondale, IL (US)
- OSTI ID:
- 6275871
- Journal Information:
- IEEE Trans. Comput.; (United States), Journal Name: IEEE Trans. Comput.; (United States) Vol. 38:3; ISSN ITCOB
- Country of Publication:
- United States
- Language:
- English
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