A fast 1-D serial-parallel systolic multiplier

Journal Article · Thu Oct 01 00:00:00 EDT 1987 · IEEE Trans. Comput.; (United States)

OSTI ID:5756724

Wu, I C

Based on the modified Booth's algorithm, a fast 1-D serial-parallel systolic multiplier is designed for multiplying two's complement numbers. The circuit with countercurrent data flow pattern accepts the multiplicand serially, the multiplier in parallel, and outputs the product serially. It requires a complementer and N/2 cells, each of which contains a ripple-carry adder and some gates, where N is restricted to even. The number of clocks required to multiply an n-bit (n less than or equal to N) multiplier and an m-bit multiplicand is equal to n + m - 1, and independent of the circuit size N.

• Research Organization: Dept. of Computer Science, Carnegie-Mellon Univ., Pittsburgh, PA 15213
• OSTI ID: 5756724
• Journal Information: IEEE Trans. Comput.; (United States), Journal Name: IEEE Trans. Comput.; (United States) Vol. C-36:10; ISSN ITCOB
• Country of Publication: United States
• Language: English

Related Subjects

99 GENERAL AND MISCELLANEOUS
990210* -- Supercomputers-- (1987-1989)
ALGORITHMS
ARRAY PROCESSORS
COMPUTER CALCULATIONS
DATA-FLOW PROCESSING
ELECTRONIC CIRCUITS
INTEGRATED CIRCUITS
MATHEMATICAL LOGIC
MICROELECTRONIC CIRCUITS
PARALLEL PROCESSING
PROGRAMMING