Algorithms for iterative array multiplication

Journal Article · Fri Aug 01 00:00:00 EDT 1986 · IEEE Trans. Comput.; (United States)

DOI:https://doi.org/10.1109/TC.1986.1676822· OSTI ID:5441231

Nakamura, S

Algorithms for the parallel multiplication of two n-bit binary numbers by an iterative array of logic cells are discussed. The regular interconnection structures of the multiplier array cell elements, which are ideal for VLSI implementation, are described. The speed and hardware complexity of two new iterative array algorithms, both of which require n-cell delays for one n-bit x n-bit multiplication, are compared to a straightforward iterative array algorithms having a 2n-cell delay and its higher radix version having an n-cell delay.

• Research Organization: Thayer School of Engineering, Dartmouth College, Hanover, NH 03755
• OSTI ID: 5441231
• Journal Information: IEEE Trans. Comput.; (United States), Journal Name: IEEE Trans. Comput.; (United States) Vol. C-35:8; ISSN ITCOB
• Country of Publication: United States
• Language: English

Related Subjects

99 GENERAL AND MISCELLANEOUS
990200* -- Mathematics & Computers
ALGORITHMS
ARRAY PROCESSORS
CIRCUIT THEORY
COMPUTERS
DIGITAL COMPUTERS
ELECTRONIC CIRCUITS
INTEGRATED CIRCUITS
ITERATIVE METHODS
MATHEMATICAL LOGIC
MICROELECTRONIC CIRCUITS
PARALLEL PROCESSING
PERFORMANCE
PROGRAMMING
SUPERCOMPUTERS
TIME DEPENDENCE