Array architectures for iterative algorithms
Journal Article
·
· Proc. IEEE; (United States)
Regular mesh-connected arrays are shown to be isomorphic to a class of so-called regular iterative algorithms. For a wide variety of problems it is shown how to obtain appropriate iterative algorithms and then how to translate these algorithms into arrays in a systematic fashion. Several ''systolic'' arrays presented in the literature are shown to be specific case of the variety of architectures that can be derived by the techniques presented here. These include arrays for Fourier Transform, Matrix Multiplication, and Sorting.
- Research Organization:
- AT and T Bell Labs., Murray Hill, NJ 07974
- OSTI ID:
- 5701432
- Journal Information:
- Proc. IEEE; (United States), Journal Name: Proc. IEEE; (United States) Vol. 75:9; ISSN IEEPA
- Country of Publication:
- United States
- Language:
- English
Similar Records
Regular iterative algorithms and their implementations on processor arrays
Systolic array architecture for convolutional decoding algorithms: Viterbi algorithm and stack algorithm
Regular iterative algorithms and their implementation on processor arrays
Thesis/Dissertation
·
Tue Dec 31 23:00:00 EST 1985
·
OSTI ID:5310887
Systolic array architecture for convolutional decoding algorithms: Viterbi algorithm and stack algorithm
Thesis/Dissertation
·
Tue Dec 31 23:00:00 EST 1985
·
OSTI ID:6891535
Regular iterative algorithms and their implementation on processor arrays
Journal Article
·
Mon Feb 29 23:00:00 EST 1988
· Proc. IEEE; (United States)
·
OSTI ID:5039754