Regular iterative algorithms and their implementations on processor arrays
Thesis/Dissertation
·
OSTI ID:5310887
It is shown that there exists a subclass of these regular iterative algorithms that is isomorphic with systolic/wavefront arrays. Given an algorithm that belongs to this subclass, certain procedures are devised for obtaining a variety of systolic array architectures for implementing the algorithm. Among the infinitely many such arrays that can be designed, some pointers are provided for making a rational choice, based on some objective criteria. If the given regular iterative algorithm is not necessarily in this subclass, then some procedures are presented for determining asymptotic lower bounds on the time required for executing the algorithm, and on the amount of storage necessary during the execution. Further, it is shown how one can derive processor array implementations of the algorithm that meet the predicted lower bounds. The procedures described for obtaining these lower bounds and for designing an implementation of the algorithm can be executed in constant time on some sequential back-end processor, independent of the number of computations in the regular iterative algorithm. The usefulness of regular iterative algorithms for various problems in signal processing, graph theory, numerical linear algebra and other scientific applications is also demonstrated in this thesis.
- Research Organization:
- Stanford Univ., CA (USA)
- OSTI ID:
- 5310887
- Country of Publication:
- United States
- Language:
- English
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