The scalable coherent interface, IEEE P1596; Status and possible applications to data acquisition and physics

Conference · Sun Apr 01 04:00:00 EDT 1990 · IEEE Transactions on Nuclear Science (Institute of Electrical and Electronics Engineers); (USA)

OSTI ID:6606351

Gustavson, D B ^[1]

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1. Stanford Linear Accelerator Center, Menlo Park, CA (USA)

IEEE P1596, the scalable coherent interface (formerly known as SuperBus) is based on experience gained while developing Fastbus (ANSI/IEEE 960--1986, IEC 935), Futurebus (IEEE P896.x) and other modern 32-bit buses. SCI goals include a minimum bandwidth of 1 GByte/sec per processor in multiprocessor systems with thousands of processors; efficient support of a coherent distributed-cache image of distributed shared memory; support for repeaters which interface to existing or future buses; and support for inexpensive small rings as well as for general switched interconnections like Banyan, Omega, or crossbar networks. This paper presents a summary of current directions, reports the status of the work in progress, and suggests some applications in data acquisition and physics.

• DOE Contract Number: AC03-76SF00515
• OSTI ID: 6606351
• Report Number(s): CONF-900143--
• Conference Information: Journal Name: IEEE Transactions on Nuclear Science (Institute of Electrical and Electronics Engineers); (USA) Journal Volume: 37:2
• Country of Publication: United States
• Language: English

Related Subjects

42 ENGINEERING
426000 -- Engineering-- Components
Electron Devices & Circuits-- (1990-)
440104* -- Radiation Instrumentation-- High Energy Physics Instrumentation
46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND TECHNOLOGY
99 GENERAL AND MISCELLANEOUS
990200 -- Mathematics & Computers
ARRAY PROCESSORS
COHERENT RADIATION
COMPUTER NETWORKS
DATA ACQUISITION
DATA PROCESSING
DISTRIBUTED DATA PROCESSING
ELECTROMAGNETIC RADIATION
ELECTRONIC CIRCUITS
FASTBUS SYSTEM
INTEGRATED CIRCUITS
INTERFACES
MEMORY DEVICES
MICROELECTRONIC CIRCUITS
PHYSICS
PROCESSING
RADIATIONS