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Applications for the scalable coherent interface

Conference · · AIP Conference Proceedings (American Institute of Physics); (USA)
OSTI ID:5954095
 [1]
  1. Stanford Linear Accelerator Center, Stanford, CA (USA)
IEEE P1596, the Scalable Coherent Interface (formerly known as SuperBus) is based on experience gained while developing Fastbus (ANSI/IEEE 960-1986, IEC 935), Futurebus (IEEE P896.x) and other modern high-performance buses. SCI goals include a minimum and bandwidth of 1 GByte/sec per processor in multiprocessor systems with thousands of processors; efficient support of a coherent distributed-cache image of distributed shared memory; support for bridges which interface to existing or future buses; and support for inexpensive small rings as well as for general switched interconnections like Banyan, Omega, or crossbar networks.
DOE Contract Number:
AC03-76SF00515
OSTI ID:
5954095
Report Number(s):
CONF-9004190--
Conference Information:
Journal Name: AIP Conference Proceedings (American Institute of Physics); (USA) Journal Volume: 209:1
Country of Publication:
United States
Language:
English