The single-chip FASTBUS slave interface
This paper reports a single-chip implementation of the general-purpose FASTBUS slave interface (FSI) developed in ECL gate-array technology. The FSI will occupy on 1.6% of the available circuit board space while providing a complete 32-bit interface to the FASTBUS. All mandatory slave-interface requirements of IEEE 960 are supported, in addition to several non-mandatory requirements and the optional, extended MS code features. Geographic, logical, and broadcast addressing are implemented using on-chip registers. An optional multiple-module addressing technique is included that allows participating modules residing on a common crate or cable segment to respond as if individually addressed in sequence.
- OSTI ID:
- 6582412
- Report Number(s):
- CONF-900143--
- Journal Information:
- IEEE Transactions on Nuclear Science (Institute of Electrical and Electronics Engineers); (USA), Journal Name: IEEE Transactions on Nuclear Science (Institute of Electrical and Electronics Engineers); (USA) Vol. 37:2; ISSN 0018-9499; ISSN IETNA
- Country of Publication:
- United States
- Language:
- English
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