The single-chip FASTBUS Slave Interface
A single-chip implementation of the general-purpose FASTBUS Slave Interface (FSI) has been developed in ECL gate-array technology. The FSI will occupy only 1.6% of the available circuit board space while providing a complete 32-bit interface to the FASTBUS. All mandatory slave-interface requirements of IEEE 960 are supported, in addition to several non-mandatory requirements and the optional, extended MS code features. Geographic, logical, and broadcast addressing are implemented using on-chip registers. An optional multiple-module addressing technique is included that allows participating modules residing on a common crate or cable segment to respond as if individually addressed in sequence. The user interface provided by the FSI allows control of slave status-response and connection timing for both address and data cycles. The BIT1 ECL array technology used for the FSI allows direct connections to the FASTBUS, eliminating the need for external driver/receiver buffers.
- Research Organization:
- Scientific Systems International Ltd., Los Alamos, NM (United States)
- Sponsoring Organization:
- USDOE, Washington, DC (United States)
- DOE Contract Number:
- AC02-87ER80454
- OSTI ID:
- 205218
- Report Number(s):
- CONF-900143--40; ON: DE96006643
- Country of Publication:
- United States
- Language:
- English
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