An integrated high performance Fastbus slave interface
- CERN/ECP, Geneva (Switzerland)
A high performance CMOS Fastbus slave interface ASIC (Application Specific Integrated Circuit) supporting all addressing and data transfer modes defined in the IEEE 960 - 1986 standard is presented. The FAstbus Slave Integrated Circuit (FASIC) is an interface between the asynchronous Fastbus and a clock synchronous processor/memory bus. It can work stand-alone or together with a 32 bit microprocessor. The FASIC is a programmable device enabling its direct use in many different applications. A set of programmable address mapping windows can map Fastbus addresses to convenient memory addresses and at the same time act as address decoding logic. Data rates of 100 MBytes/sec to Fastbus can be obtained using an internal FIFO in the FASIC to buffer data between the two buses during block transfers. Message passing from Fastbus to a microprocessor on the slave module is supported. A compact (70 mm x 170 mm) Fastbus slave piggy back sub-card interface including level conversion between ECL and TTL signal levels has been implemented using surface mount components and the 208 pin FASIC chip.
- OSTI ID:
- 5946162
- Report Number(s):
- CONF-921005--
- Journal Information:
- IEEE Transactions on Nuclear Science (Institute of Electrical and Electronics Engineers); (United States), Journal Name: IEEE Transactions on Nuclear Science (Institute of Electrical and Electronics Engineers); (United States) Vol. 40:4 part 1; ISSN 0018-9499; ISSN IETNAE
- Country of Publication:
- United States
- Language:
- English
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46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND TECHNOLOGY
COMMUNICATIONS
COMPUTERS
DATA PROCESSING
DATA TRANSMISSION
ELECTRONIC CIRCUITS
EQUIPMENT INTERFACES
FASTBUS SYSTEM
HIGH ENERGY PHYSICS
INTEGRATED CIRCUITS
MEASURING INSTRUMENTS
MICROELECTRONIC CIRCUITS
MICROPROCESSORS
PERFORMANCE
PHYSICS
PROCESSING
RADIATION DETECTORS