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Radiation-hardened silicon-gate CMOS/SOS

Conference · · IEEE Trans. Nucl. Sci.; (United States)
OSTI ID:6544311

High performance, radiation hardened silicon gate CMOS/SOS circuits have been fabricated. Radiation hardness was achieved by using a low temperature (875/sup 0/C), wet-process gate oxide, and by minimizing the temperature of subsequent process steps. The need for additional temperature steps was eliminated by in-situ doping of the polysilicon gate material with boron and by using ion-implantation instead of diffusions to form source and drain regions. Radiation effects in simple inverter circuits have been measured. Threshold shifts after 10/sup 6/ rads (Si) of ionizing radiation are less than or equal to 0.5 V for n-channel transistors and less than or equal to 1.6 V for p-channel transistors. Irradiation of p-channel transistors in circuit configurations where effective positive gate voltages occur, results in a 4 V shift at 10/sup 6/ rads (Si). Ring oscillator circuits have been fabricated to measure intrinsic circuit performance. With a 15 V power supply, stage delays of 0.5 ns are achieved. These short stage delays verify the suitability of the fabrication process for high speed circuit applications.

Research Organization:
Rockwell International Corp., Anaheim, CA
OSTI ID:
6544311
Journal Information:
IEEE Trans. Nucl. Sci.; (United States), Journal Name: IEEE Trans. Nucl. Sci.; (United States) Vol. NS-24:6; ISSN IETNA
Country of Publication:
United States
Language:
English