Investigation of radiation effects and hardening procedures for CMOS/SOS
Ionizing radiation effects and hardening procedures have been investigated using simple CMOS/SOS circuits fabricated with SiO$sub 2$ gate insulators. A modified gate oxidation process using steam and HC l has resulted in improved gate oxide hardness - with threshold voltage shifts of less than two volts up to a total dose of 10$sup 6$ rads(Si). Radiation-induced n-channel leakage currents were reduced by more than two orders of magnitude by using a deep boron ion implant and appropriate processing techniques. Post-irradiation values of less than 0.5$mu$A/mil have been obtained using this procedure. Studies of charge buildup at the silicon-sapphire interface indicate an effective positive charge in the range of 10$sup 11$ cm$sup -2$ to 10$sup 12$ cm$sup -2$- peaking at a total dose of about 10$sup 5$ rads(Si). This effective charge decreases for increasing doses above 5 x 10$sup 5$ rads(Si). The decrease is attributed to radiation-induced interface sttates. (auth)
- Research Organization:
- Rockwell International, Anaheim, CA
- NSA Number:
- NSA-33-020346
- OSTI ID:
- 4090006
- Journal Information:
- IEEE Trans. Nucl. Sci., v. NS-22, no. 6, pp. 2185-2189, Journal Name: IEEE Trans. Nucl. Sci., v. NS-22, no. 6, pp. 2185-2189; ISSN IETNA
- Country of Publication:
- United States
- Language:
- English
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