Skip to main content
U.S. Department of Energy
Office of Scientific and Technical Information

Radiation hardened 64-bit CMOS/SOS RAM

Conference · · IEEE Trans. Nucl. Sci.; (United States)
OSTI ID:7213066

Radiation hardening procedures have been implemented in design, analysis and fabrication of a 64-bit CMOS/SOS RAM. The resultant circuit is a moderately complex (714 transistor), dielectrically isolated integrated circuit which features high performance and high radiation tolerance. Typical electrical parameters include 12..pi.. nsec read-access time and 1..mu..watt/bit standby power dissipation. The SOS construction minimizes radiation-induced transient photocurrents while a hardened gate insulator provides immunity to total dose effects. Transient radiation upset levels exceed 3 x 10/sup 10/ rads(Si)/sec for short (less than or equal to 50 ns) pulses and ionizing dose hardness exceeds 10/sup 6/ rads(Si). A neutron fluence of 3.65 x 10/sup 14/ n/cm/sup 2/ had no effect on circuit operation beyond that expected from the ionizing radiation alone.

Research Organization:
Rockwell International Corp., Anaheim, CA
OSTI ID:
7213066
Journal Information:
IEEE Trans. Nucl. Sci.; (United States), Journal Name: IEEE Trans. Nucl. Sci.; (United States) Vol. NS-23:6; ISSN IETNA
Country of Publication:
United States
Language:
English