Improvement on radiation-hardened MOS device technology

Technical Report · Mon Dec 31 23:00:00 EST 1984

OSTI ID:6532883

Hatano, H

In order to design radiation-hardened MOS LSI's for space and nuclear plant applications, improvement on radiation-hardened MOS integrated circuit designs is discussed, based on gamma-ray irradiation test results for basic CMOS logic circuits and CMOS shift register circuits. Post-radiation logic thresholds for basic CMOS inverters and post-radiation propagation delay times for 19-stage CMOS ring oscillators were successfully predicted by circuit simulation, based on experimental NMOS and PMOS V(TH) shift data, including gate bias dependence during irradiation. Utilizing the circuit simulation, the DC noise immunity for three-input NAND was found to be 36% greater than for the three-input NOR. The gate area for the optimized NAND is about three times smaller than that for the optimized NOR. Static and dynamic circuit performance degradations are also discussed, based on MOS FET parameter shifts due to radiation effects, using gamma-ray-irradiated CMOS shift registers. New NMOS transistor structure introduction into radiation-hardened bulk CMOS circuit designs, in which no parasitic field transistors are formed under the NMOS gate edges, was investigated.

• Research Organization: Research and Development Association for Future Electron Devices, Tokyo (Japan)
• OSTI ID: 6532883
• Report Number(s): PB-85-236974/XAB
• Country of Publication: United States
• Language: English

Related Subjects

42 ENGINEERING
420800 -- Engineering-- Electronic Circuits & Devices-- (-1989)
440200* -- Radiation Effects on Instrument Components
Instruments
or Electronic Systems
46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND TECHNOLOGY
ELECTRONIC CIRCUITS
FIELD EFFECT TRANSISTORS
HARDENING
INTEGRATED CIRCUITS
LOGIC CIRCUITS
MICROELECTRONIC CIRCUITS
MOS TRANSISTORS
MOSFET
PHYSICAL RADIATION EFFECTS
RADIATION EFFECTS
RADIATION HARDENING
SEMICONDUCTOR DEVICES
TRANSISTORS