CMOS/SOS NAND gate sapphire photocurrrent compensation

Conference · Mon Dec 01 04:00:00 EST 1975 · IEEE Trans. Nucl. Sci., v. NS-22, no. 6, pp. 2617-2620

OSTI ID:4094717

Phillips, D H

The analysis summarized below is applicable to the design of radiation- hardened CMOS/SOS NAND gates, having any number of inputs. Derivations and general solutions have been developed to allow the consideration of any combination of input logic signals. This analysis method can be extended to CMOS/ SOS NOR gates and is directly applicable to CMOS/SOS inverters when the NAND gate model is exercised as a single-input circuit. Silicon-on-sapphire construction greatly reduces junction photocurrents in MOS circuits. However, a ''resistive'' current path through the normally insulating sapphire substrate can occur due to radiation-induced carrier generation in the sapphire. Current flowing through this photoresistive path accounts for most of the SOS transistor drain photocurrent observed experimentally. This analysis develops design rules for optimizing the dose-rate radiation hardness of CMOS/SOS digital NAND gates including SOS photoconduction effects. The work reported herein extends the application of existing sapphire photocurrent compensation methods. (auth)

• Research Organization: Rockwell International Corp., Anaheim, CA
• NSA Number: NSA-33-020353
• OSTI ID: 4094717
• Conference Information: Journal Name: IEEE Trans. Nucl. Sci., v. NS-22, no. 6, pp. 2617-2620
• Country of Publication: United States
• Language: English

Related Subjects

*GATING CIRCUITS-- RADIATION HARDENING
*INTEGRATED CIRCUITS-- RADIATION HARDENING
*MOS TRANSISTORS-- RADIATION HARDENING
440200* --Instrumentation--Radiation Effects on Instrument Components
Instruments
or Electronic Systems
DESIGN
EQUIVALENT CIRCUITS
FAILURES
LEAKAGE CURRENT
N46300* --Instrumentation--Radiation Effects on Instrument Components
Instruments
or Electronic Systems
TRANSISTORS