Silicon barrier Josephson junction configuration
Patent
·
OSTI ID:6531543
A planar, silicon barrier, Josephson junction and method of forming the junction which does not require expensive highresolution, lithography techniques such as electron beam or xray. The method includes an etching mask-etch process which forms the basic structure configuration using a (110)-cut silicon wafer. Subsequent to the etching process the mask is removed and a superconducting film is deposited on the previously formed silicon surface to produce a single crystal silicon barrier with good electrical properties.
- Assignee:
- Secretary of the Navy
- Patent Number(s):
- US 4368479
- OSTI ID:
- 6531543
- Country of Publication:
- United States
- Language:
- English
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