New developments in segment ancillary logic for FASTBUS
Conference
·
OSTI ID:6520653
Segment Ancillary Logic hardware for FASTBUS systems provides logical functions required in common by all devices attached to a segment. It controls the execution of arbitration cycles, and geographical address cycles, and generates the system handshake responses for broadcast operations. The mandatory requirements for Segment Ancillary Logic in the FASTBUS specifications are reviewed. A detaifled implementation based on ECL logic is described, and the hardware to be used on an ECL cable segment for an experimental FASTBUS system at SLAC is shown.
- Research Organization:
- Stanford Linear Accelerator Center, CA (USA)
- DOE Contract Number:
- AC03-76SF00515
- OSTI ID:
- 6520653
- Report Number(s):
- SLAC-PUB-2990; CONF-821011-48; ON: DE83007010
- Country of Publication:
- United States
- Language:
- English
Similar Records
New developments in segment ancillary logic for FASTBUS
The single-chip FASTBUS slave interface
The single-chip FASTBUS Slave Interface
Journal Article
·
Mon Jan 31 23:00:00 EST 1983
· IEEE Trans. Nucl. Sci.; (United States)
·
OSTI ID:5914045
The single-chip FASTBUS slave interface
Conference
·
Sat Mar 31 23:00:00 EST 1990
· IEEE Transactions on Nuclear Science (Institute of Electrical and Electronics Engineers); (USA)
·
OSTI ID:6582412
The single-chip FASTBUS Slave Interface
Conference
·
Sun Dec 30 23:00:00 EST 1990
·
OSTI ID:205218
Related Subjects
440104* -- Radiation Instrumentation-- High Energy Physics Instrumentation
46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND TECHNOLOGY
ELECTRONIC CIRCUITS
EQUIPMENT INTERFACES
FASTBUS SYSTEM
LOGIC CIRCUITS
NATIONAL ORGANIZATIONS
SPECIFICATIONS
STANFORD LINEAR ACCELERATOR CENTER
US DOE
US ERDA
US ORGANIZATIONS
46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND TECHNOLOGY
ELECTRONIC CIRCUITS
EQUIPMENT INTERFACES
FASTBUS SYSTEM
LOGIC CIRCUITS
NATIONAL ORGANIZATIONS
SPECIFICATIONS
STANFORD LINEAR ACCELERATOR CENTER
US DOE
US ERDA
US ORGANIZATIONS