New developments in segment ancillary logic for FASTBUS
Journal Article
·
· IEEE Trans. Nucl. Sci.; (United States)
Segment Ancillary Logic hardware for FASTBUS systems provides logical functions required in common by all devices attached to a segment. It controls the execution of arbitration cycles, and geographical address cycles, and generates the system handshake responses for broadcast operations. The mandatory requirements for Segment Ancillary Logic in the FASTBUS specifications are reviewed. A detailed implementation based on ECL logic is described, and the hardware to be used on an ECL cable segment for an experimental FASTBUS system at SLAC is shown.
- Research Organization:
- Stanford Linear Accelerator Center, Stanford University, Stanford, CA 94305
- DOE Contract Number:
- AC03-76SF00515
- OSTI ID:
- 5914045
- Journal Information:
- IEEE Trans. Nucl. Sci.; (United States), Journal Name: IEEE Trans. Nucl. Sci.; (United States) Vol. 30:1; ISSN IETNA
- Country of Publication:
- United States
- Language:
- English
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