A wavefront algorithm for LU decomposition of a partitioned matrix on VLSI processor arrays
The authors discuss problems of how to handle larger matrices on an array of a given size (m/sub o/ X m/sub o/), and develop a wavefront-driven algorithm that utilizes the array for distributed computations. As a basis, we the authors assume that the size m/sub o/ X m/sub o/ of the array is already fairly large, m/sub o/ = 64, 128, 256, etc., even though individual VLSI chips are limited to housing arrays that are far smaller. Construction of arrays with basic VLSI chips is a major research topic and should be pursued separately. In this connection the authors proposed a ''Series-Parallel Bus'' scheme. Whatever sizes they have invested in array hardwares, they may be confronted with still larger matrices. The authors' algorithms are designed to contain data-movement computation within the array in order to avoid I/O bottleneck, but with additional costs of some data-store registers at individual PEs. Separation of data loading from computation may be too conservative an approach for maximum utilization of concurrency in matrix computations. The authors suggest the ''Wavefront Data-Loading'' scheme, a detailed discussion of which is deferred to subsequent papers, as is discussion of implementation issues of hardware and software.
- Research Organization:
- Dept. of Circuits and Systems, Faculty of Engineering, Hiroshima Univ., Higashi-Hiroshima 724
- OSTI ID:
- 6505942
- Journal Information:
- J. Parallel Distrib. Comput.; (United States), Journal Name: J. Parallel Distrib. Comput.; (United States) Vol. 3:2; ISSN JPDCE
- Country of Publication:
- United States
- Language:
- English
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Related Subjects
990210* -- Supercomputers-- (1987-1989)
ALGORITHMS
ARRAY PROCESSORS
CIRCUIT THEORY
COMPUTER-AIDED DESIGN
DATA-FLOW PROCESSING
DIFFERENTIAL EQUATIONS
ELECTRONIC CIRCUITS
EQUATIONS
GAUSSIAN PROCESSES
INTEGRATED CIRCUITS
MATHEMATICAL LOGIC
MATRICES
MICROELECTRONIC CIRCUITS
PARTIAL DIFFERENTIAL EQUATIONS
PROGRAMMING
WAVE EQUATIONS