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Single event upsets in gallium arsenide dynamic logic

Conference · · IEEE Transactions on Nuclear Science (Institute of Electrical and Electronics Engineers); (United States)
OSTI ID:6488790
 [1];  [2]; ; ;  [3]
  1. Naval Postgraduate School, Monterey, CA (United States). ECE Dept.
  2. SFA Inc., Landover, MD (United States)
  3. Naval Research Lab., Washington, DC (United States)

The advantages and disadvantages of using gallium arsenide (GaAs) dynamic logic in computers and digital systems are briefly discussed, especially with respect to space applications. A short introduction to the topology and operation of GaAs Two-Phase Dynamic FET Logic (TDFL) circuits is presented. Experiments for testing the SEU sensitivity of GaAs TDFL, using a laser to create charge collection events, are described. Results are used to estimate the heavy-ion, soft error rate for TDFL in a spacecraft in geosynchronous orbit, and the dependence of the SEU sensitivity on clock frequency, clock voltage, and clock phase. Analysis of the data includes a comparison between the SEU sensitivities of TDFL and the more common static form of GaAs logic, Directly Coupled FET Logic (DCFL). This is the first reported SEU testing of GaAs dynamic logic.

OSTI ID:
6488790
Report Number(s):
CONF-940726--
Journal Information:
IEEE Transactions on Nuclear Science (Institute of Electrical and Electronics Engineers); (United States), Journal Name: IEEE Transactions on Nuclear Science (Institute of Electrical and Electronics Engineers); (United States) Vol. 41:6Pt1; ISSN 0018-9499; ISSN IETNAE
Country of Publication:
United States
Language:
English