Extraction of MOS VLSI circuit models including critical interconnect parasitics
As the feature sizes of Very-Large-Scale-Integrated (VLSI) circuits continue to decrease, the timing performance of a design cannot be estimated accurately without introducing the signal delay due to interconnect parasitics. Modeling interconnect parasitics directly from a circuit layout is therefore emphasized. In this research, two programs, FEMRC and HPEX, were developed to investigate the following areas: (1) interconnect modeling, (2) hierarchical parasitic-circuit extraction, and (3) collapsing technique for interconnects. The FEMRC is a two-dimensional, finite-element program that computes the resistance or the capacitance from the user-specified geometry. Since the equation formulation for FEMRC is based on a finite-element method, there is not shape restrictions on dielectric interfaces or conductor geometries. The program HPEX is a hierarchical parasitic circuit extractor which takes the CIF layout description as an input and generates a SPICE input with different details of interconnect parasitics. In this extractor, analytical formulas fitted from numerical data are used to model interconnect parasitics of VLSI circuits in order to compromise between the accuracy and the computation time.
- Research Organization:
- Illinois Univ., Urbana (USA)
- OSTI ID:
- 6445548
- Country of Publication:
- United States
- Language:
- English
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Related Subjects
420800 -- Engineering-- Electronic Circuits & Devices-- (-1989)
99 GENERAL AND MISCELLANEOUS
990210* -- Supercomputers-- (1987-1989)
COMPUTER CODES
ELECTRONIC CIRCUITS
FINITE ELEMENT METHOD
FUNCTIONAL MODELS
INTEGRATED CIRCUITS
MICROELECTRONIC CIRCUITS
NOISE
NUMERICAL SOLUTION
SIGNAL DISTORTION