The effects of interconnection parasitics on VLSI circuit performance
An analysis of the delays caused by interconnections in VLSI integrated circuits is presented, examining the effects metal resistance and silicon conduction have on signal propagation. This analysis makes use of a metal-insulator-semiconductor (MIS) microstrip model. The computation techniques used require that any transistor driving an interconnection be modeled as a voltage source with a linear impedance. A graphical technique, originally developed by L. Bergeron, is presented which shows that the correct value of this impedance is given by the transistor's large-signal drain impedance. (This had not previously been defined.) Analysis of the step response computations, with experimental verification, shows that signal propagation in VLSI interconnections can usually be described by quasi-TEM propagation if the length is less that one millimeter, or by slow-wave propagation if the length is longer. Also examined is the extent to which metal resistance effects these interconnection delays. It is seen that metal resistance is not yet a problem for aluminum interconnections up to 1 cm in length and that the use of lower resistivity metals cannot be expected to appreciably enhance the speed of such interconnections.
- Research Organization:
- Stanford Univ., CA (USA)
- OSTI ID:
- 5692698
- Country of Publication:
- United States
- Language:
- English
Similar Records
Impact and limitations of interconnect technology on VLSI and restructurable VLSI design
A comparison of lossy and superconducting interconnect for computers
Related Subjects
990200* -- Mathematics & Computers
ALUMINIUM
ELECTRIC CONDUCTIVITY
ELECTRICAL PROPERTIES
ELECTRONIC CIRCUITS
ELEMENTS
INTEGRATED CIRCUITS
JOINTS
MATERIALS
MATHEMATICAL MODELS
METALS
MICROELECTRONIC CIRCUITS
PERFORMANCE
PHYSICAL PROPERTIES
SEMICONDUCTOR DEVICES
SEMICONDUCTOR MATERIALS
TIME DELAY
TRANSISTORS
VERIFICATION