Radiation effects in advanced microelectronics technologies
- California Inst. of Tech., Pasadena, CA (United States). Jet Propulsion Lab.
The pace of device scaling has increased rapidly in recent years. Experimental CMOS devices have been produced with feature sizes below 0.1 {micro}m, demonstrating that devices with feature sizes between 0.1 and 0.25 {micro}m will likely be available in mainstream technologies after the year 2000. This paper discusses how the anticipated changes in device dimensions and design are likely to affect their radiation response in space environments. Traditional problems, such as total dose effects, SEU and latchup are discussed, along with new phenomena. The latter include hard errors from heavy ions (microdose and gate-rupture errors), and complex failure modes related to advanced circuit architecture. The main focus of the paper is on commercial devices, which are displacing hardened device technologies in many space applications. However, the impact of device scaling on hardened devices is also discussed.
- Sponsoring Organization:
- National Aeronautics and Space Administration, Washington, DC (United States)
- OSTI ID:
- 644128
- Report Number(s):
- CONF-970934--
- Journal Information:
- IEEE Transactions on Nuclear Science, Journal Name: IEEE Transactions on Nuclear Science Journal Issue: 3Pt3 Vol. 45; ISSN 0018-9499; ISSN IETNAE
- Country of Publication:
- United States
- Language:
- English
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