Technologies and processes for radiation-hardened CMOS
Hardening of integrated circuits against the effects of radiation exposure involves circuit design, circuit layout, technology features and dimensions, and processing techniques. This paper discusses technology features and processing techniques that have been employed at Sandia National Laboratories to develop two silicon gate CMOS technologies that are hardened to total dose and transient radiation environments. These technologies have minimum feature sizes of 3 ..mu..m and 1.5 ..mu..m, respectively and have been employed to fabricate a variety of circuits of LSI and VLSI complexity. The relationship between the technology features and the process techniques and the resulting degradation in radiation environments will be explored.
- Research Organization:
- Sandia National Labs., Albuquerque, NM (USA)
- DOE Contract Number:
- AC04-76DP00789
- OSTI ID:
- 6394754
- Report Number(s):
- SAND-85-2414C; ON: DE86007148
- Country of Publication:
- United States
- Language:
- English
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Related Subjects
Instruments
or Electronic Systems
46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND TECHNOLOGY
ELECTRONIC CIRCUITS
ELEMENTS
HARDENING
INTEGRATED CIRCUITS
MICROELECTRONIC CIRCUITS
MOS TRANSISTORS
PHYSICAL RADIATION EFFECTS
RADIATION EFFECTS
RADIATION HARDENING
SEMICONDUCTOR DEVICES
SEMIMETALS
SILICON
TRANSISTORS