Expert system for VLSI layout

Thesis/Dissertation · Thu Jan 01 04:00:00 EST 1987

OSTI ID:6178131

Lin, Y L.S.

This thesis addresses the problem of automatic-layout generation for the random-logic modules in a VLSI chip. A new top-down methodology, especially when the number of fixed-shaped modules is large, is proposed. A new path-selection heuristic search algorithm is proposed for finding the minimum rectilinear tree in a rectilinear-geometry graph. In the search process, the active terminals are modeled as magnets. Unlike previous search algorithms, which divided a multi-terminal net connection into several independent pair connections, this algorithm considers the existence of the active terminals during the path-searching process. Two commonly used tree-connection algorithms were used experimentally. The algorithm is shown experimentally to be better than those produced by the other search algorithms which do not consider the active terminals. The idea of a path selection heuristic search algorithm can also be applied to a Lee-type expansion algorithm by assigning each fringe vertex x a value f(x) = g(x) - i(x). The small attractive force produced by the active vertices can be precalculated by grid processors for hardware routers, so that a much-faster execution speed can be obtained.

• Research Organization: Illinois Univ., Urbana (USA)
• OSTI ID: 6178131
• Country of Publication: United States
• Language: English

Related Subjects

99 GENERAL AND MISCELLANEOUS
990210* -- Supercomputers-- (1987-1989)
ALGORITHMS
DESIGN
ELECTRONIC CIRCUITS
EXPERT SYSTEMS
INTEGRATED CIRCUITS
MATHEMATICAL LOGIC
MICROELECTRONIC CIRCUITS
PERFORMANCE