Vertex upgrading problems for VLSI
Thesis/Dissertation
·
OSTI ID:5359569
The author examines vertex modification (splitting, deleting and upgrading) problems that arise in VLSI CAD and other application areas. The problems he considers differ from previously studied vertex-deletion problems in that he is interested in modifying vertices in a dag so that the resulting dag has no path whose length exceeds a prespecified amount. Vertex-modification problems can be used to model the scan register placement problem in VLSI design, placement of signal boosters in lossy circuits, satellite uplink/downlink placement in communication networks, etc. The approach adopted is to first determine which of these problems are NP-hard. Pseudo polynomial time algorithms and fast heuristics for the NP-hard versions are explored. Fast polynomial time algorithms for other versions are developed. Experimentation using the ISCAS benchmark circuits are also performed.
- Research Organization:
- Minnesota Univ., Minneapolis, MN (United States)
- OSTI ID:
- 5359569
- Country of Publication:
- United States
- Language:
- English
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