Algorithms for VLSI CAD
This thesis deals with the development of heuristic methods for NP-complete problems and fast algorithms for problems for which high degree polynomial time algorithms are known. The problem size in a typical VLSI design is growing rapidly. This makes the performance of algorithms, with high degree polynomial time complexity, unacceptable in the real world. Specifically, following problems are studied. A class of heuristics called General Adaptive Heuristics is formulated. Traditionally, methods like classical pairwise exchange heuristic, have been used. Recently, simulated annealing has been proposed as a heuristic for combinatorial optimization. Unlike the classical pairwise exchange heuristic, simulated annealing accepts bad perturbations. Another method called sequence heuristics is proposed which like annealing, accepts bad as well as good perturbations. These experiments were performed on VAX, Apollo, and Cray systems. An efficient algorithm for net extraction is developed. A two phase approach is adopted. In the first phase, a scan line based pair generator uses the polygon and layer pairs information to construct pairs of polygons with real overlaps. A fast algorithm is developed to detect overlap between arbitrary polygons. These algorithms have been programmed in Fortran on a Sperry 1192 system.
- Research Organization:
- Minnesota Univ., Minneapolis (USA)
- OSTI ID:
- 6910189
- Country of Publication:
- United States
- Language:
- English
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