Algorithms for VLSI layout
This thesis considers several problems arising during VLSI layout and presents new techniques for solving them efficiently. A linear-time algorithm is proposed for generating a planar layout of a planar graph with n vertices. The vertices are represented by horizontal line segments and the edges by vertical line segments. This layout occupies an area at most n by 2n - 4 and contains no bends. Next, the author investigates two variants of this representation and presents characterizations of the classes of graphs that admit such representations. Furthermore, he presents linear time algorithms for testing the existence of and for constructing visibility representations. He also considers planar embeddings, where vertices are mapped to grid points and edges are mapped to pair-wise nonintersecting grid paths. The problem of wiring a given layout in a uniform grid is a fundamental problem in VLSI layout. A systematic approach to wiring layouts in the octo-square grid is presented. This approach is based on the concept of two-colorable maps. Algorithms for obtaining the wiring of a layout run in time linear with respect to the area occupied by the layout were developed.
- Research Organization:
- Illinois Univ., Urbana, IL (USA)
- OSTI ID:
- 5501454
- Resource Relation:
- Other Information: Thesis (Ph. D.)
- Country of Publication:
- United States
- Language:
- English
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