Compaction-based VLSI layout
Generally speaking, a compaction based VLSI layout system consists of two major parts: (1) a symbolic editor which maintains explicit connectivity and structural information about the circuit; (2) a compactor which translates the high level description of a circuit to the detailed layout needed for fabrication and tries to make as compact a layout as Possible without violating any design rules. Instead of developing a complete compaction based VLSI layout system, this thesis presents some theoretical concepts and several new compaction techniques, such as scan line based approach, which can either cooperate with a symbolic editor to form a layout system or work as a post-process step to improve the results obtained by an existing layout system. Also, some compaction related problems are solved and proposed. Based on the special property of channel routing, the author presents a geometric method for channel compaction. For a given channel routing topology, the minimum channel height is always achieved with the incorporation of sliding contacts and automatically inserting necessary jogs. The geometric compaction approach is then generalized and applied to compact the entire VLSI chip at the building-block level. With a systematic way of automatic jog insertion, he proves that under the given layout topology and design rules, the lower bound of one dimensional compaction with automatic jog insertion is achieved by the geometric compaction algorithm. A new simultaneous two-dimensional compaction algorithm is developed primarily for placement refinement of building-block layout. The algorithm is based on a set of defined graph operations on a mixed adjacency graph for a given placement. The mixed-adjacency graph can be updated efficiently if the placement is represented by tiles in the geometric domain.
- Research Organization:
- California Univ., Berkeley, CA (USA)
- OSTI ID:
- 6223173
- Country of Publication:
- United States
- Language:
- English
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