Layouts for the shuffle-exchange graph and lower bound techniques for VLSI
The thesis is divided into two parts. In the first part, we describe and analyze several new VLSI layouts for the shuffle-exchange graph. These include (1) an asymptotically optimal, area layout for the N-mode shuffle-exchange graph, and (2) several practical layouts for small shuffle-exchange graphs. The new layouts require substantially less area than previously known layouts and can serve as the basis for designing large scale shuffle-exchange chips. In the second part of thee thesis, we develop general methods for proving lower bounds on the layout area, crossing number, bisection width and maximum edge length of VLSI networks. The area results indicate that some graphs with O(s. rt. of N)-separators (and, in particular, some planar graphs) do not have linear-area layouts, thus disproving a popular conjecture. The edge length bounds indicate that the layouts of some networks must have very long wires (possibly as long as the width of the layout).
- Research Organization:
- Massachusetts Inst. of Tech., Cambridge (USA). Lab. for Computer Science
- OSTI ID:
- 6745123
- Report Number(s):
- AD-A-121538/3
- Country of Publication:
- United States
- Language:
- English
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