Parallel processor

Patent · Tue Mar 21 04:00:00 EST 1989

OSTI ID:6140199

Hillis, W D

A processor array is described for a parallel computer comprising: an array of processor memories, each of which comprises a memory means into which data is written and from which data is read and a processor for producing an output dependent at least in part on data read from the memory means and instruction information, and means for interconnecting the processor/memories of an array in an n-dimensional pattern having at least 2/sup n/ nodes through which data is routed from any processor/memory in the array to any other processor/memory, n being greater than 2. The interconnecting means consist of means for generating an addressed message packet that is routed from one processor/memory to another in the n-dimensional pattern in accordance with address information included in the message packet, the address information being a relative address comprising as many digits as there are dimensions, each digit representing the relative displacement of the message packet from the node to which it is addressed, and means at each node in the n-dimensional pattern for routing the message packet in accordance with the address information in the packet.

• Assignee: NOV; EDB-89-106139; NOV-89-059048
• Patent Number(s): US 4814973
• OSTI ID: 6140199
• Country of Publication: United States
• Language: English

Related Subjects

99 GENERAL AND MISCELLANEOUS
990210* -- Supercomputers-- (1987-1989)
ARRAY PROCESSORS
COMPUTER ARCHITECTURE
COMPUTERS
DIGITAL COMPUTERS
MEMORY DEVICES
PARALLEL PROCESSING
PROGRAMMING
SUPERCOMPUTERS