Binary tree parallel processor

Patent · Tue Aug 22 04:00:00 EDT 1989

OSTI ID:5346410

Stolfo, S J; Miranker, D P

This paper describes a parallel processor array. It comprises: a plurality of processing elements, each comprising: a processor having an arithmetic logic unit, control store, program sequences and instruction decoder; a read/write memory associated with the processor; an input/output means associated with the processor and read/write memory; means for interconnecting the processing elements in a binary tree in which each processing element except those at extremities of the binary tree is connected to one parent processing element and at least first and second child processing elements. The input/output means comprising: means for broadcasting information received from a parent processing element to the child processing elements, such that common information is distributed to each processing element of the binary tree or a subtree thereof without direct control of the processors of the processing elements; and means for determining a priority among respective values of information received from the child processing elements and information received from the processor with which the input/output means is associated without direct control of the processors of the processing elements.

• Assignee: Trustees of Columbia Univ. in the City of New York, NY
• Patent Number(s): US 4860201
• Application Number: PPN: US 6-902547A
• OSTI ID: 5346410
• Country of Publication: United States
• Language: English

Related Subjects

99 GENERAL AND MISCELLANEOUS
990200* -- Mathematics & Computers
ARRAY PROCESSORS
COMMUNICATIONS
COMPUTER ARCHITECTURE
COMPUTERS
DATA TRANSMISSION
DIGITAL COMPUTERS
MEMORY MANAGEMENT
PARALLEL PROCESSING
PROGRAMMING
SUPERCOMPUTERS