Parallel processor/memory circuit

Patent · Tue Nov 24 04:00:00 EST 1987

OSTI ID:5635753

Hillis, W D; Knight, Jr, T F; Bawden, A; Kahle, B L; Chapman, D; Christman, D P; Lasser, C A; Feynman, C R

An array of processor/memories is described comprising: an instruction decoder that generates tables of outputs in response to instructions received at the decoder, processor/memories each of which comprises a memory means into which data may be written and from which data may be read and a processor for producing an output depending at least in part on data read from the memory means and instruction information received at the instruction decoder. The processor/memories are fabricated on a single chip of semiconductive material; means for simultaneously addressing at least one cell in each of the memory means either to write data thereto or read data therefrom; means for providing as an input to each processor the data read from its associated memory means; means for providing to each processor the output tables from the decoder, the output tables specifying all possible outputs for the different combinations of inputs to the processor; and means in each processor for selecting as the output from the processor that output in the output table that corresponds to the data input to the processor.

• Assignee: NOV; NOV-88-092032; EDB-88-047325
• Patent Number(s): US 4709327
• OSTI ID: 5635753
• Country of Publication: United States
• Language: English

Related Subjects

99 GENERAL AND MISCELLANEOUS
990210* -- Supercomputers-- (1987-1989)
ARRAY PROCESSORS
COMPUTER ARCHITECTURE
DATA PROCESSING
DESIGN
MEMORY DEVICES
PARALLEL PROCESSING
PROCESSING
PROGRAMMING
SEMICONDUCTOR DEVICES