Method and apparatus for interconnecting processors in a hyper-dimensional array
Patent
·
OSTI ID:6215322
This patent describes a parallel processor having an array of integrated circuits, each being addressed by a multibit binary address and comprising at least one processor and being interconnected to each of its nearest neighbors in a pattern of a Boolean cube of more than three dimensions, apparatus for interconnecting the integrated circuits on boards and backplanes comprising: means for interconnecting on each circuit board the integrated circuits which are nearest neighbors in dimensions one through L; means for interconnecting on each backplane the integrated circuits which are nearest neighbors in dimensions L+1 through M; means for interconnecting from one backplane to another the integrated circuits which are nearest neighbors in dimensions M+1 through N; and means for adjusting the clock cycle during the routing of messages between processors in accordance with the dimension of the processors between which the message is being routed.
- Assignee:
- Thinking Machines Corp., Cambridge, MA
- Patent Number(s):
- US 4805091
- OSTI ID:
- 6215322
- Country of Publication:
- United States
- Language:
- English
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