A Josephson systolic array processor for multiplication/addition operations

Conference · Fri Mar 01 04:00:00 EST 1991 · IEEE Transactions on Magnetics (Institute of Electrical and Electronics Engineers); (United States)

OSTI ID:6092654

Morisue, M; Li, F Q; Tobita, M; Kaneko, S ^[1]

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1. Dept. of Electronic Engineering, Saitama Univ., Urawa (JP)

A novel Josephson systolic array processor to perform multiplication/addition operations is proposed. The systolic array processor proposed here consists of a set of three kinds of interconnected cells of which main circuits are made by using SQUID gates. A multiplication of 2 bits by 2 bits is performed in the single cell at a time and an addition of three data with two bits is simultaneously performed in an another type of cell. Furthermore, information in this system flows between cells in a pipeline fashion so that a high performance can be achieved. In this paper the principle of Josephson systolic array processor is described in detail and the simulation results are illustrated for the multiplication/addition of (4 bits {times} 4 bits + 8 bits). The results show that these operations can be executed in 330ps.

• OSTI ID: 6092654
• Report Number(s): CONF-900944--
• Conference Information: Journal Name: IEEE Transactions on Magnetics (Institute of Electrical and Electronics Engineers); (United States) Journal Volume: 27:2
• Country of Publication: United States
• Language: English

Related Subjects

665411 -- Basic Superconductivity Studies-- (1992-)
665412* -- Superconducting Devices-- (1992-)
75 CONDENSED MATTER PHYSICS
SUPERCONDUCTIVITY AND SUPERFLUIDITY
99 GENERAL AND MISCELLANEOUS
990200 -- Mathematics & Computers
ARRAY PROCESSORS
COMPUTER CALCULATIONS
COMPUTERIZED SIMULATION
DESIGN
ELECTRONIC EQUIPMENT
EQUIPMENT
FLUXMETERS
JOSEPHSON JUNCTIONS
JUNCTIONS
MEASURING INSTRUMENTS
MICROWAVE EQUIPMENT
SIMULATION
SQUID DEVICES
SUPERCONDUCTING DEVICES
SUPERCONDUCTING JUNCTIONS