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U.S. Department of Energy
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High-speed memory-circuit design and system integration

Thesis/Dissertation ·
OSTI ID:6043185
The overall performance of high-speed computer systems is often governed by memory characteristics such as access time, power dissipation and scale of integration. These characteristics are, in turn, functions of both the performance of the individual memory chips and the packaging environment in which those chips are embedded. This research has led to the successful design and integration of a novel two-port BiCMOS static memory cell that combines ECL-level word line voltage swings and emitter-follower bit line coupling with a static CMOS latch for data storage. With this cell it has been possible to achieve access times comparable to those of high-speed bipolar static memories, while preserving the high density and low power of CMOS memory arrays. The memory cell can be read and written simultaneously through independent read and write ports, thus making it especially well-suited to those applications where high-speed operation and multiport access are required at the same time. A READ access time of 3.8 nsec has been achieved at room temperature in an experimental 4K {times} 1bit memory integrated in a 1.5{mu}m, 5GHz BiCMOS technology. This circuit dissipates only 520 mW and the cell area is only 30% larger than a conventional CMOS six-transistor cell. Moreover, the access time of the circuit is relatively insensitive to temperature, increasing to 4 nsec at a case temperature of 100C. If future systems are to fully exploit the continuing improvements in performance achievable with scaled VLSI technology, substantial improvements in system integration methods are essential. In this work, an active substrate' approach to system integration is proposed.
Research Organization:
Stanford Univ., CA (United States)
OSTI ID:
6043185
Country of Publication:
United States
Language:
English

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