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U.S. Department of Energy
Office of Scientific and Technical Information

High-speed nonvolatile CMOS/MNOS RAM

Conference ·
OSTI ID:6099599

A bulk silicon technology for a high-speed static CMOS/MNOS RAM has been developed. Radiation-hardened, high voltage CMOS circuits have been fabricated for the memory array driving circuits and the enhancement-mode p-channel MNOS memory transistors have been fabricated using a native tunneling oxide with a 45 nm CVD Si/sub 3/N/sub 4/ insulator deposited at 750/sup 0/C. Read cycle times less than 350 ns and write cycle times of 1 ..mu..s are projected for the final 1Kx1 design. The CMOS circuits provide adequate speed for the write and read cycles and minimize the standby power dissipation. Retention times well in excess of 30 min are projected.

Research Organization:
Sandia Labs., Albuquerque, NM (USA)
DOE Contract Number:
EY-76-C-04-0789
OSTI ID:
6099599
Report Number(s):
SAND-79-0603C; CONF-790809-1
Country of Publication:
United States
Language:
English