An on-chip smart memory for a data-flow CPU

Journal Article · Wed Jan 31 23:00:00 EST 1990 · IEEE Journal of Solid-State Circuits (Institute of Electrical and Electronics Engineers); (USA)

DOI:https://doi.org/10.1109/4.50289· OSTI ID:5758046

Uvieghara, G A; Nakagome, Y ^[1]; Jeong, D K ^[2]; Hodges, D A ^[3]

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1. Hitachi Ltd., Kokubunji, Tokyo (Japan). Central Research Lab.
2. Texas Instruments, Inc., Dallas, TX (USA)
3. California Univ., Berkeley, CA (USA). Dept. of Electrical Engineering and Computer Sciences

Register Alias Table (RAT) is a smart memory that is embedded in HPSm (High-Performance Substrate), a Berkeley data-flow CPU. It is a multiport memory that has content addressability and support for branch prediction and exception handling, in addition to conventional (small caps) read and (small caps) write operations. An experimental 1240-bit smart memory chip is implemented in a 1.6-{mu}m double-metal scalable CMOS process. This memory performs 15 operations within a cycle time of 100 ns, has 34 658 transistors, occupies in an area of 3.8 mm {times} 5.2 mm, and dissipates 0.51 W.

• OSTI ID: 5758046
• Journal Information: IEEE Journal of Solid-State Circuits (Institute of Electrical and Electronics Engineers); (USA), Journal Name: IEEE Journal of Solid-State Circuits (Institute of Electrical and Electronics Engineers); (USA) Vol. 25:1; ISSN IJSCB; ISSN 0018-9200
• Country of Publication: United States
• Language: English

Related Subjects

42 ENGINEERING
426000 -- Engineering-- Components
Electron Devices & Circuits-- (1990-)
99 GENERAL AND MISCELLANEOUS
990200* -- Mathematics & Computers
DATA-FLOW PROCESSING
MEMORY DEVICES
MOS TRANSISTORS
PROGRAMMING
SEMICONDUCTOR DEVICES
TRANSISTORS