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U.S. Department of Energy
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Reevaluating the worst-case radiation response of MOS transistors

Conference ·
OSTI ID:5982009

Predicting worst-case response of a semiconductor device to ionizing radiation is a formidable challenge. As processes change and MOS gate insulators become thinner in advanced VLSI and VHSIC technologies, failure mechanisms must be constantly re-examined. This series of Vugraphs presents results of a recent study in which more than 100 MOS transistors were monitored for up to 300 days after Co-60 exposure. Based on these results, a reevaluation of ''worst-case'' n-channel transistor response (most positive threshold voltage shift) in low-dose-rate and postirradiation environments is required in many cases. In this presentation it is shown for Sandia hardened n-channel transistors with a 32 nm gate oxide, that switching from zero-volt bias, held during the entire radiation period, to positive bias during anneal clearly leads to a more positive threshold voltage shift (and thus the slowest circuit response) after Co-60 exposure than the standard case of maintaining positive bias during irradiation and anneal. We conclude that irradiating these kinds of transistors with zero-volt bias, and annealing with positive bias, leads to worst-case postirradiation response. For commercial devices (with few interface states at doses of interest), on the other hand, device response only improves postirradiation, and worst-case response (in terms of device leakage) is for devices irradiated under positive bias and annealed with zero-volts bias. 2 refs., 9 figs.

Research Organization:
Sandia National Labs., Albuquerque, NM (USA)
DOE Contract Number:
AC04-76DP00789
OSTI ID:
5982009
Report Number(s):
SAND-87-1001C; CONF-8708137-1-Vugraphs; ON: DE87014157
Country of Publication:
United States
Language:
English