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A reevaluation of worst-case postirradiation response for hardened MOS transistors

Conference · · IEEE Trans. Nucl. Sci.; (United States)
OSTI ID:7202040

The ''worst-case'' postirradiation response of Sandia hardened n-channel transistors following Co-60 exposure to total dose levels of system interest is demonstrated to occur for zero-volt bias during radiation, and positive bias during a subsequent anneal. This observation is explained in terms of oxide-trapped and interface-state charge buildup and anneal. Additional results are presented which suggest that, for future technologies with very thin gate oxides, worst-case device leakage during irradiation may well occur for zero-volt irradiations. These results highlight the importance of periodically reevaluating the response of MOS devices during and after irradiation to determine worst-case test conditions, particularly as technologies advance and gate insulators become thinner.

Research Organization:
Sandia National Labs., P.O. Box 5800, Albuquerque, NM (US)
OSTI ID:
7202040
Report Number(s):
CONF-8707112-
Journal Information:
IEEE Trans. Nucl. Sci.; (United States), Journal Name: IEEE Trans. Nucl. Sci.; (United States) Vol. NS-34:6; ISSN IETNA
Country of Publication:
United States
Language:
English