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CMOS/SOI hardening at 100 MRAD (SiO sub 2 )

Conference · · IEEE Transactions on Nuclear Science (Institute of Electrical and Electronics Engineers); (USA)
OSTI ID:5884267
; ; ; ;  [1]; ;
  1. CEA, de Bruyeres-le-Chatel, BP-12, F-91680 Bruyeres-le-Chatel (FR)

Hardened CMOS/SOI 29101 microprocessor, elementary cells and transistor shave been irradiated at levels between 10 Mrad(SiO{sub 2}) and 1 Grad(SiO{sub 2}) ({sup 60}Co and 10 keV x-rays). SIMOX buried oxide behavior in the range of 100 Mrad(SiO{sub 2}) and a channel-stopped MOS/SOI structure avoiding lateral leakage current are presented. These two items indicate the feasibility of a CMOS/SOI technology operating in the hundred Mrad(SiO{sub 2}) range.

OSTI ID:
5884267
Report Number(s):
CONF-900723--
Journal Information:
IEEE Transactions on Nuclear Science (Institute of Electrical and Electronics Engineers); (USA), Journal Name: IEEE Transactions on Nuclear Science (Institute of Electrical and Electronics Engineers); (USA) Vol. 37:6; ISSN 0018-9499; ISSN IETNA
Country of Publication:
United States
Language:
English

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