Simulation of SEU transients in CMOS ICs

Conference · Sun Dec 01 04:00:00 EST 1991 · IEEE Transactions on Nuclear Science (Institute of Electrical and Electronics Engineers); (United States)

OSTI ID:5832205

Kaul, N; Bhuva, B L; Kerns, S E ^[1]

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1. Space Electronics Research Group, Vanderbilt Univ., Nashville, TN (US)

This paper reports that available analytical models of the number of single-event-induced errors (SEU) in combinational logic systems are not easily applicable to real integrated circuits (ICs). An efficient computer simulation algorithm set, SITA, predicts the vulnerability of data stored in and processed by complex combinational logic circuits to SEU. SITA is described in detail to allow researchers to incorporate it into their error analysis packages. Required simulation algorithms are based on approximate closed-form equations modeling individual device behavior in CMOS logic units. Device-level simulation is used to estimate the probability that ion-device interactions produce erroneous signals capable of propagating to a latch (or n output node), and logic-level simulation to predict the spread of such erroneous, latched information through the IC. Simulation results are compared to those from SPICE for several circuit and logic configurations. SITA results are comparable to this established circuit-level code, and SITA can analyze circuits with state-of-the-art device densities (which SPICE cannot). At all IC complexity levels, SITAS offers several factors of 10 savings in simulation time over SPICE.

• OSTI ID: 5832205
• Report Number(s): CONF-910751--
• Conference Information: Journal Name: IEEE Transactions on Nuclear Science (Institute of Electrical and Electronics Engineers); (United States) Journal Volume: 38:6
• Country of Publication: United States
• Language: English

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