An SEU-hardened CMOS data latch design
Conference
·
· IEEE Trans. Nucl. Sci.; (United States)
OSTI ID:6065443
A Single Event Upset (SEU)-hardened Complementary Metal-Oxide Semiconductor (CMOS) data latch design is described. The hardness is achieved by virtue of the latch design, thus no fabrication process or design groundrule development is required. Hardness is gained with comparatively little adverse impact on performance. Cyclotron tests provided hardness verification.
- Research Organization:
- IBM Corp., Systems Integration Div., Manassas, VA (US)
- OSTI ID:
- 6065443
- Report Number(s):
- CONF-880730-
- Journal Information:
- IEEE Trans. Nucl. Sci.; (United States), Journal Name: IEEE Trans. Nucl. Sci.; (United States) Vol. 35:6; ISSN IETNA
- Country of Publication:
- United States
- Language:
- English
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Related Subjects
440200 -- Radiation Effects on Instrument Components
Instruments
or Electronic Systems
46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND TECHNOLOGY
654001* -- Radiation & Shielding Physics-- Radiation Physics
Shielding Calculations & Experiments
73 NUCLEAR PHYSICS AND RADIATION PHYSICS
ACCELERATORS
BREMSSTRAHLUNG
CYCLIC ACCELERATORS
CYCLOTRON RADIATION
CYCLOTRONS
DESIGN
ELECTROMAGNETIC RADIATION
HARDENING
MOS TRANSISTORS
PHYSICAL RADIATION EFFECTS
RADIATION EFFECTS
RADIATION HARDENING
RADIATIONS
SEMICONDUCTOR DEVICES
TRANSISTORS
VERIFICATION
Instruments
or Electronic Systems
46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND TECHNOLOGY
654001* -- Radiation & Shielding Physics-- Radiation Physics
Shielding Calculations & Experiments
73 NUCLEAR PHYSICS AND RADIATION PHYSICS
ACCELERATORS
BREMSSTRAHLUNG
CYCLIC ACCELERATORS
CYCLOTRON RADIATION
CYCLOTRONS
DESIGN
ELECTROMAGNETIC RADIATION
HARDENING
MOS TRANSISTORS
PHYSICAL RADIATION EFFECTS
RADIATION EFFECTS
RADIATION HARDENING
RADIATIONS
SEMICONDUCTOR DEVICES
TRANSISTORS
VERIFICATION