Systolic temporal arithmetic: A new formalism for specification, verification, and synthesis of systolic arrays
Thesis/Dissertation
·
OSTI ID:5815995
A novel formalism, termed Systolic Temporal Arithmetic (STA), is introduced. It provides necessary constructs to describe arithmetic operations in dynamic environments. The motivation behind the development of STA is to use it for systolic array design at the array architecture level. It is particularly useful for formally specifying systolic array designs, and for formally verifying their correctness with respect to the algorithm specifications. Besides providing value and operation abstractions from the lower level, the formalism exploits unique systolic features such as synchrony, regularity, repeatability, modularity, pipelinability, parallel processing ability, as well as spatial and temporal locality, to provide constructs and verification techniques for simple, efficient, and effective systolic array specification verification. STA overcomes many limitations of current specification and verification techniques. It can be used with lower level formalism for multilevel reasoning of systolic arrays. Application examples are given to show how STA can be applied to specify and verify several different systolic arrays. To present a more unified design environment, STA is also extended to describe systolic array synthesis process. A synthesis procedure for systolic arrays is presented which also includes an algorithm transformation technique developed that can improve the computation time of resulting arrays for suitable algorithms, without much increase in area requirement. Several systolic array synthesis examples are also provided in this dissertation.
- Research Organization:
- Southwestern Louisiana Inst., Lafayette, LA (USA)
- OSTI ID:
- 5815995
- Country of Publication:
- United States
- Language:
- English
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