Mapping nested loop algorithms into multidimensional systolic arrays

Journal Article · Mon Jan 01 04:00:00 EST 1990 · IEEE Transactions on Parallel and Distributed Systems; (USA)

DOI:https://doi.org/10.1109/71.80125· OSTI ID:6445904

Lee, P Z ^[1]; Kedem, Z M ^[2]

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1. Institute of Information Science, Academia Sinica (TW)
2. Dept. of Computer Science, Courant Institute of Mathematical Sciences, New York Univ., New York, NY (US)

This paper is concerned with transforming depth p-nested for loop algorithms into q-dimensional systolic VLSI arrays where 1 {le} q {le} p {minus} 1. Previously there existed complete characterizations of correct transformations only for the cases when q = p {minus} 1 or q = 1. The authors fill in this gap by giving formal necessary and sufficient conditions for correct transformation of a p-nested loop algorithm into a q-dimensional systolic array for any q, 1 {le} q {le} p {minus} 1. They also provide practical methods to derive optimal or suboptimal systolic array implementations. They apply the techniques developed by us to the automatic design of special purpose and programmable systolic arrays. The author's results also contribute towards automatic compilation onto more general purpose programmable arrays. Synthesis of linear and planar systolic array implementations for a three-dimensional cube-graph algorithm and a reindexed Warshall-Floyd pathfinding algorithm is used to illustrate our method.

• OSTI ID: 6445904
• Journal Information: IEEE Transactions on Parallel and Distributed Systems; (USA), Journal Name: IEEE Transactions on Parallel and Distributed Systems; (USA) Vol. 1:1; ISSN ITDSE; ISSN 1045-9219
• Country of Publication: United States
• Language: English

Related Subjects

99 GENERAL AND MISCELLANEOUS
990200* -- Mathematics & Computers
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IMPLEMENTATION
INTEGRATED CIRCUITS
MANY-DIMENSIONAL CALCULATIONS
MATHEMATICAL LOGIC
MICROELECTRONIC CIRCUITS
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PARALLEL PROCESSING
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