Systolic temporal arithmetic; A new formalism for specification and verification of systolic arrays

Journal Article · Wed Aug 01 04:00:00 EDT 1990 · IEEE Transations on Computer-Aided Design of Integrated Circuits and Systems; (USA)

DOI:https://doi.org/10.1109/43.57788· OSTI ID:6502474

Ling, N ^[1]; Bayoumi, M A ^[2]

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1. Dept. of Electrical Engineering and Computer Science, Santa Clara Univ., Santa Clara, CA (US)
2. Center for Advanced Computer Studies, Univ. of Southwestern Louisiana, Lafayette, LA (US)

This paper introduces a novel formalism named systolic temporal arithmetic (STA) suitable for describing arithmetic operations in dynamic environments. The motivation behind the development of STA is to use it for formal specifications and verifications of systolic arrays at the array architecture level. Besides providing value and operation abstraction from the lower level, it also exploits several features of systolic arrays such as synchrony, regularity, repeatability, modularity, pipelinability, parallel processing ability, as well as spatial and temporal locality. STA provides constructs and verification techniques for simple, efficient, and effective systolic array specification and verification. Verification techniques such as mathematical induction are suggested to exploit these systolic array features so as to speedup the process.

• OSTI ID: 6502474
• Journal Information: IEEE Transations on Computer-Aided Design of Integrated Circuits and Systems; (USA), Journal Name: IEEE Transations on Computer-Aided Design of Integrated Circuits and Systems; (USA) Vol. 9:8; ISSN ITCSD; ISSN 0278-0070
• Country of Publication: United States
• Language: English

Related Subjects

99 GENERAL AND MISCELLANEOUS
990200* -- Mathematics & Computers
ARRAY PROCESSORS
COMPUTER ARCHITECTURE
COMPUTER CALCULATIONS
COMPUTERS
DIGITAL COMPUTERS
FAULT TOLERANT COMPUTERS
SPECIFICATIONS