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Title: Multiprocessor communication method and apparatus

Patent ·
OSTI ID:5790766

In a computer system wherein N processors, each having a unique identity code, communicate with one another over a system bus and control of the system bus resides in one of the processors at any point in time, an apparatus is described for synchronizing communication between the processors. It consists of: N bus master control means for controllably coupling the N processors to the system bus, N separate storage means, each of which is coupled to a different one of the N processors and to the system bus independently of the associated bus master control means, request register means coupled to the system bus and to an associated processor and responsive to the request signal for storing the request data present in the request signal whenever the identity code of the associated processor is present in the request address of the request signal, wherein each request register means comprise first means for detecting the presence of the identity code of the associated processor in the request address and for generating an write enable signal in response thereto; a first N-bit register wherein each bit position corresponds uniquely to one of the N processors in the computer system; and first means for evaluating the request data to determine the identity of the sending processor and for setting the bit corresponding to the sending processor in the N-bit register whenever the first detecting means generates the write enable signal; and acknowledgment register means coupled to the system bus and to the associated processor N communication buffer means each of which is coupled to a different sending processor and to the system bus independently of the associated bus master control means.

Assignee:
Ramtek Corp., Santa Clara, CA
Patent Number(s):
US 4698746
OSTI ID:
5790766
Resource Relation:
Patent File Date: Filed date 25 May 1983
Country of Publication:
United States
Language:
English