Multiprocessor interface device
A multiprocessor interface device is described comprising: a random access memory; first and second processor interfaces, each having a port for connection to a corresponding processor, each of the processor interfaces comprising a bidirectional address/data bus for bidirectionally connecting address or data information between the corresponding processor and the multiprocessor interface device, a processor control bus for receiving control signals from the corresponding processor. The received control signals include at least an access request control signal; an interface control bus for transmitting control signals to the corresponding processor. The transmitted control signals include at least a ready control signal having a first logic state indicating that access to the random access memory is granted, and having a second logic state indicating that access to the random access memory is not granted; and an address pointer register, connected to the bidirectional address/data bus, connected to the random access memory, and addressable by the corresponding processor, for storing address information; an arbitration latch connected to the random access memory. The first processor interface and the second processor interface for connecting only one of the first and second processor interfaces to the random access memory, causing the one processor interface to transmit its ready control signal at the first logic state to the corresponding processor indicating access is granted, and causing the other processor interface to transmit its ready control signal at the second logic state to the corresponding processor, an address equal detector, connected to the address pointer registers of the first processor interface and to the address pointer register of the second processor interface.
- Assignee:
- Texas Instruments Incorporated, Dallas, TX
- Patent Number(s):
- US 4698753
- OSTI ID:
- 6011121
- Country of Publication:
- United States
- Language:
- English
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